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ST93CS46 st93cs47 1k (64 x 16) serial microwire eeprom not for new design june 1997 1/16 this is information on a product still in production bu t not recommended for new de signs. ai00884b d v cc ST93CS46 st93cs47 v ss cq pre w s figure 1. logic diagram 1 million erase/write cycles, with 40 years data retention self-timed programming cycle with auto-erase ready/busy signal during programming single supply voltage 3v to 5.5v for the ST93CS46 2.5v to 5.5v for the st93cs47 user defined write protected area page write mode (4 words) sequential read operation 5ms typical programming time ST93CS46 and st93cs47 are replaced by the m93s46 description the ST93CS46 and st93cs47 are 1k bit electri- cally erasable programmable memory (eeprom) fabricated with sgs-thomson's high endurance single polysilicon cmos technology. the memory is accessed through a serial input d and output q. the 1k bit memory is organized as 64 x 16 bit words.the memory is accessed by a set of instruc- tions which include read, write, page write, write all and instructions used to set the memory protec- tion. a read instruction loads the address of the first word to be read into an internal address pointer. s chip select input d serial data input q serial data output c serial clock pre protect enable w write enable v cc supply voltage v ss ground table 1. signal names 8 1 so8 (m) 150mil width 8 1 psdip8 (b) 0.4mm frame
description (cont'd) the data is then clocked out serially. the address pointer is automatically incremented after the data is output and, if the chip select input (s) is held high, the ST93CS46/47 can output a sequential stream of data words. in this way, the memory can be read as a data stream of 16 to 1024 bits, or continuously as the address counter automatically rolls over to 00 when the highest address is reached. within the time required by a program- ming cycle (t w ), up to 4 words may be written with the help of the page write instruction; the whole memory may also be erased, or set to a predeter- mined pattern, by using the write all instruction. within the memory, an user defined area may be protected against further write instructions. the size of this area is defined by the content of a v ss q w pre c sv cc d ai00885b ST93CS46 st93cs47 1 2 3 4 8 7 6 5 figure 2a. dip pin connections 1 v ss q w pre c sv cc d ai00886c ST93CS46 st93cs47 2 3 4 8 7 6 5 figure 2b. so pin connections symbol parameter value unit t a ambient operating temperature 40 to 85 c t stg storage temperature 65 to 150 c t lead lead temperature, soldering (so8 package) (psdip8 package) 40 sec 10 sec 215 260 c v io input or output voltages (q = v oh or hi-z) 0.3 to v cc +0.5 v v cc supply voltage 0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) (2) 3000 v electrostatic discharge voltage (machine model) (3) 500 v notes: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the sgs-thomson sure program and other relevant quality documents. 2. mil-std-883c, 3015.7 (100pf, 1500 w ). 3. eiaj ic-121 (condition c) (200pf, 0 w ). table 2. absolute maximum ratings (1) protect register, located outside of the memory array. as a final protection step, data may be per- manently protected by programming a one time programing bit (otp bit) which locks the protect register content. programming is internally self-timed (the external clock signal on c input may be disconnected or left running after the start of a write cycle) and does not require an erase cycle prior to the write instruc- tion. the write instruction writes 16 bits at one time into one of the 64 words, the page write instruction writes up to 4 words of 16 bits to sequential loca- tions, assuming in both cases that all addresses are outside the write protected area. after the start of the programming cycle, a ready/busy signal is available on the data output (q) when the chip select (s) input pin is driven high. 2/16 ST93CS46, st93cs47
input rise and fall times 20ns (10% to 90%) input pulse voltages 0.4v to 2.4v input and output timing reference voltages 0.8 and 2v ac measurement conditions note that output hi-z is defined as the point where data is no longer driven. ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc figure 3. ac testing input output waveforms symbol parameter test condition min max unit c in input capacitance v in =0v 5 pf c out output capacitance v out =0v 5 pf note: 1. sampled only, not 100% tested. table 3. capacitance (1) (t a =25 c, f = 1 mhz ) symbol parameter test condition min max unit i li input leakage current 0v v in v cc 2.5 m a i lo output leakage current 0v v out v cc , q in hi-z 2.5 m a i cc supply current (ttl inputs) s = v ih , f = 1 mhz 3 ma supply current (cmos inputs) s = v ih , f = 1 mhz 2 ma i cc1 supply current (standby) s = v ss ,c=v ss 50 m a v il input low voltage (ST93CS46,47) 4.5v v cc 5.5v 0.1 0.8 v input low voltage (ST93CS46) 3v v cc 5.5v 0.1 0.2 v cc v input low voltage (st93cs47) 2.5v v cc 5.5v 0.1 0.2 v cc v v ih input high voltage (ST93CS46,47) 4.5v v cc 5.5v 2 v cc +1 v input high voltage (ST93CS46) 3v v cc 5.5v 0.8 v cc v cc +1 v input high voltage (st93cs47) 2.5v v cc 5.5v 0.8 v cc v cc +1 v v ol output low voltage i ol = 2.1ma 0.4 v i ol =10 m a 0.2 v v oh output high voltage i oh = 400 m a 2.4 v i oh = 10 m av cc 0.2 v table 4. dc characteristics (t a = 0 to 70 c or 40 to 85 c; v cc = 3v to 5.5v for ST93CS46 and v cc = 2.5v to 5.5v for st93cs47) 3/16 ST93CS46, st93cs47
symbol alt parameter test condition min max unit t prvch t pres protect enable valid to clock high 50 ns t wvch t pes write enable valid to clock high 50 ns t shch t css chip select high to clock high 50 ns t dvch t dis input valid to clock high 100 ns t chdx t dih clock high to input transition 100 ns t chql t pd0 clock high to output low 500 ns t chqv t pd1 clock high to output valid 500 ns t clprx t preh clock low to protect enable transition 0 ns t slwx t peh chip select low to write enable transition 250 ns t clsl t csh clock low to chip select transition 0 ns t slsh t cs chip select low to chip select high note 1 250 ns t shqv t sv chip select high to output valid 500 ns t slqz t df chip select low to output hi-z 300 ns t chcl t skh clock high to clock low note 2 250 ns t clch t skl clock low to clock high note 2 250 ns t w t wp erase/write cycle time 10 ms f c f sk clock frequency 0 1 mhz notes: 1. chip select must be brought low for a minimum of 250 ns (t slsh ) between consecutive instruction cycles. 2. the clock frequency specification calls for a minimum clock period of 1 m s, therefore the sum of the timings t chcl +t clch must be greater or equal to 1 m s. for example, if t chcl is 250 ns, then t clch must be at least 750 ns. table 5. dc characteristics (t a = 0 to 70 c or 40 to 85 c; v cc = 3v to 5.5v for ST93CS46 and v cc = 2.5v to 5.5v for st93cs47) pre w c s d op code op code start start op code input tchdx tdvch tshch tclch tchcl twvch tprvch ai00887 figure 4. synchronous timing, start and op-code input 4/16 ST93CS46, st93cs47
figure 5. synchronous timing, read or write ai00820c c d q address input hi-z tdvch tclsl a0 s data output tchqv tchdx tchql an tslsh tslqz q15/q7 q0 pre w c s d hi-z tw tdvch ai00888b q tclprx tslwx tclsl tchdx tslsh tslqz busy tshqv ready write cycle address/data input an a0/d0 5/16 ST93CS46, st93cs47
power-on data protection in order to prevent data corruption and inadvertent write operations during power up, a power on reset (por) circuit resets all internal programming circuitry and sets the device in the write disable mode. when v cc reaches its functional value, the device is properlyreset (in the write disable mode) and is ready to decode and execute an incoming instruction. a stable v cc must be applied before any logic signal. instructions the ST93CS46/47 has eleven instructions, as shown in table 6. each instruction is preceded by the rising edge of the signal applied on the chip select (s) input (assuming that the clock c is low), followed by a '1' read on d input during the rising edge of the clock c. the op-codes of the instruc- tions are made up of the 2 following bits. some instructions use only these first two bits, others use also the first two bits of the address field to define the op-code. the address field is six bits long (a5-a0). the ST93CS46/47 is fabricated in cmos technol- ogy and is therefore able to run from zero hz (static input signals) up to the maximum ratings (specified in table 5). read the read instruction (read) outputs serial data on the data output (q). when a read instruction is received, the instruction and address are de- coded and the data from the memory is transferred into an output shiftregister. a dummy '0' bit is output first followed by the 16 bit word with the msb first. instruction description w pin (1) pre pin op code address (1) data additional information read read data from memory x '0' 10 a5-a0 q15-q0 write write data to memory '1' '0' 01 a5-a0 d15-d0 write is executed if the address is not inside the protected area pawrite page write to memory '1' '0' 11 a5-a0 d15-d0 write is executed if all the addresses are not inside the protected area wrall write all memory '1' '0' 00 01xxxx d15-d0 write all data if the protect register is cleared wen write enable '1' '0' 00 11xxxx wds write disable x '0' 00 00xxxx prread protect register read x '1' 10 xxxxxx q8-q0 data output = protect register content + protect flag bit prwrite protect register write '1' '1' 01 a5-a0 data above specified address a5-a0 are protected prclear protect register clear '1' '1' 11 11 1111 protect flag is also cleared (cleared flag = 1) pren protect register enable '1' '1' 00 11xxxx prds protect register disable '1' '1' 00 000000 otp bit is set permanently note: 1. x = don't care bit. table 6. instruction set 6/16 ST93CS46, st93cs47
output data changes are triggered by the low to high transition of the clock (c). the ST93CS46/47 will automatically increment the address and will clock out the next word as long as the chip select input (s) is held high. in this case the dummy '0' bit is not output between words and a continuous stream of data can be read. write enable and write disable the write enable instruction (wen) authorizes the following write instructions to be executed, the write disable instruction (wds) disables the exe- cution of the following erase/write instructions. when power is first applied, the ST93CS46/47 enters the disable mode. when the write enable instruction (wen) is executed, write instructions remain enabled until a write disable instruction (wds) is executed or if the power-on reset circuit becomes active due to a reduced v cc . to protect the memory contents from accidental corruption, it is advisable to issue the wds instruction after every write cycle. the read instruction is not affected by the wen or wds instructions. write the write instruction (write) is followed by the address and the word to be written. the write enable signal (w) must be held high during the write instruction. data input d is sampled on the low to high transition of the clock. after the last data bit has been sampled, chip select (s) must be brought low before the next rising edge of the clock (c), in order to start the self-timed program- ming cycle, providing that the address is not in the protected area. if the ST93CS46/47 is still per- forming the programming cycle, the busy signal (q = 0) will be returned if the chip select input (s) is driven high, and the ST93CS46/47 will ignore any data on the bus. when the write cycle is completed, the ready signal (q = 1) will indicate (if s is driven high) that the ST93CS46/47 is ready to receive a new instruction. page write a page write instruction (pawrite) contains the first address to be written followed by up to 4 data words. the write enable signal (w) must be held high duringthe write instruction. input address and data are read on the low to high transition of the clock. after the receipt of each data word, bits a1-a0 of the internal address register are incre- mented, the high order bits a5-a2 remaining un- changed. users must take care by software to ensure that the last word address has the same four upper order address bits as the initial address transmitted to avoid address roll-over. after the lsb of the last data word, chip select (s) must be brought low before the next rising edge of the clock (c). the falling edge of chip select (s) initiates the internal, self-timed write cycle. the page write operation will not be performed if any of the 4 words is addressing the protected area. if the ST93CS46/47 is still performing the program- ming cycle, the busy signal (q = 0) will be returned if the chip select input (s) is driven high, and the ST93CS46/47 will ignore any data on the bus. when the write cycle is completed, the ready signal (q = 1) will indicate (if s is driven high) that the ST93CS46/47 is ready to receive a new instruc- tion. write all the write all instruction (wrall) is valid only after the protect register has been cleared by executing a prclear (protect register clear) instruction. the write all instruction simultaneously writes the whole memory with the same data word included in the instruction. the write enable signal (w) must be held high before and during the write instruc- tion. input address and data are read on the low to high transition of the clock. if the ST93CS46/47 is still performing the programming cycle, the busy signal (q = 0) will be returned if the chip select input (s) is driven high, and the ST93CS46/47 will ignore any data on the bus. when the write cycle is completed, the ready signal (q = 1) will indicate (if s is driven high) that the ST93CS46/47 is ready to receive a new instruction. memory write protection and protect register the ST93CS46/47 offers a protect register con- taining the bottom address of the memory area which has to be protected against write instruc- tions. in addition to this protect register, two flag bits are used to indicate the protect register status: the protect flag enabling/disabling the protection of theprotect register and the otp bit which, when set, disables access to the protect register and thus prevents any further modifications of this pro- tect register value. the content of the protect register is defined when using the prwrite in- struction, it may be read when using the prread instruction. a specific instruction pren (protect register enable) allows the user to execute the protect instructions prclear, prwrite and prds; this pren instruction being used together with the signals applied on the input pins pre (protect register enable pin) and w (write en- able). 7/16 ST93CS46, st93cs47
ai00889d 110an a0 qn q0 data out d s q s write addr op code 1 0 an a0 data in d q op code dn d0 1 busy ready s write enable 1 0 xn x0 d op code 1 01 s write disable 1 0 xn x0 d op code 00 0 check status addr pre read pre w pre w pre figure 6. read, write, wen, wds sequences 8/16 ST93CS46, st93cs47
ai00890c s page write 1 1 an a0 data in d q op code dn d0 1 busy ready check status addr pre w s write all 1 0 xn x0 data in d q op code dn d0 0 busy ready check status addr pre w 01 figure 7. pawrite, wrall sequences 9/16 ST93CS46, st93cs47
accessing the protect register is done by execut- ing the following sequence: wen: execute the write enable instruction, pren: execute the pren instruction, prwrite, prclear or prds: the protection then may be defined, in terms of size of the protected area (prwrite, prclear) and may be set permanently (prds instruction). protect register read the protect register read instruction (prread) outputs on the data output q the content of the protect register, followed by the protect flag bit. the protect register enable pin (pre) must be driven high before and during the instruction. as in the read instruction a dummy '0' bit is output first. since it is not possible to distinguish if the protect register is cleared (all 1's) or if it is written with all 1's, user must check the protect flag status (and not the protect register content) to ascertain the setting of the memory protection. protect register enable the protect register enable instruction (pren) is used to authorize the use of further prclear, prwrite and prds instructions. the pren insruction does not modify the protect flag bit value. note: a write enable (wen) instruction must be executed before the protect enable instruction. both the protect enable (pre) and write enable (w) input pins must be held high during the instruc- tion execution. protect register clear the protect register clear instruction (prclear) clears the address stored in the protect register to all 1's, and thus enables the execution of write and wrall instructions. the protect register clear execution clears the protect flag to '1'. both the protect enable (pre) and write enable (w) input pins must be driven high during the instruc- tion execution. note: a pren instruction must immediately pre- cede the prclear instruction. protect register write the protect register write instruction (prwrite) is used to write into the protect register the ad- dress of the first word to be protected. after the prwrite instruction execution, all memory loca- tions equal to and above the specified address, are protected from writing. the protect flag bit is set to '0', it can be read with protect register read instruction. both the protect enable (pre) and write enable (w) input pins must be driven high during the instruction execution. note: a pren instruction must immediately pre- cede the prwrite instruction, but it is not neces- sary to execute first a prclear. protect register disable the protect register disable instruction sets the one time programmable bit (otp bit). the protect register disable instruction (prds) is a one time only instruction which latches the protect regis- ter content, this content is therefore unalterable in the future. both the protect enable (pre) and write enable (w) input pins must be driven high during the instruction execution. the otp bit cannot be directly read, it can be checked by reading the content of the protect register (prread instruc- tion), then by writing this same value into the pro- tect register (prwrite instruction): when the otp bit is set, the ready/busy status cannot ap- pear on the data output (q); when the otp bit is not set, the busy status appear on the data output (q). a pren instruction must immediately precede the prds instruction. ready/busy status when the ST93CS46/47 is performing the write cycle, the busy signal (q = 0) is returned if s is driven high, and the ST93CS46/47 will ignore any data on the bus. when the write cycle is completed, the ready signal (q = 1) will indicate, if s is driven high, that the ST93CS46/47 is ready to receive a new instruction. once the ST93CS46/47 is ready, the data output q is set to '1' until a new start bit is decoded or the chip select is brought low. common i/o operation the data output (q) and data input (d) signals can be connected together, through a current limiting resistor, to form a common, one wire data bus. some precautions must be taken when operating the memory with this connection, mostly to prevent a short circuit between the last entered address bit (a0) and the first data bit output by q. the reader should refer to the sgs-thomson application note omicrowire eeprom common i/o opera- tiono. memory write protection (cont'd) 10/16 ST93CS46, st93cs47
ai00891d 110 xn x0 data out d s q s protect register write addr op code 1 0 an a0 d q op code 1 busy ready s protect register enable 1 0 xn x0 d op code 1 01 check status addr pre protect register read pre w pre w an a0 f f = protect flag figure 8. prread, prwrite, pren sequences 11/16 ST93CS46, st93cs47
ai00892c s protect register clear 11 d q op code 1 busy ready check status addr pre w 111 s protect register disable 10 d q op code 0 busy ready check status addr pre w 000 figure 9. prclear, prds sequences 12/16 ST93CS46, st93cs47
ordering information scheme operating voltage 46 3v to 5.5v 47 2.5v to 5.5v package b psdip8 0.4 mm frame m so8 150mil width temp. range 1 0 to 70 c 6 40 to 85 c 3 (1) 40 to 125 c option 013tr tape & reel packing example: ST93CS46 m 1 013tr note: 1. temperature range on request only. devices are shipped from the factory with the memory content set at all o1'so (ffffh). for a list of available options (operating voltage, package, etc...) or for further information on any aspect of this device, please contact the sgs-thomson sales office nearest to you. 13/16 ST93CS46, st93cs47
psdip-a a2 a1 a l e1 d e1 e n 1 c ea eb b1 b symb mm inches typ min max typ min max a 4.80 0.189 a1 0.70 0.028 a2 3.10 3.60 0.122 0.142 b 0.38 0.58 0.015 0.023 b1 1.15 1.65 0.045 0.065 c 0.38 0.52 0.015 0.020 d 9.20 9.90 0.362 0.390 e 7.62 0.300 e1 6.30 7.10 0.248 0.280 e1 2.54 0.100 ea 8.40 0.331 eb 9.20 0.362 l 3.00 3.80 0.118 0.150 n8 8 cp 0.10 0.004 psdip8 drawing is not to scale psdip8 - 8 pin plastic skinny dip, 0.4mm lead frame 14/16 ST93CS46, st93cs47
so-a e n cp b e a d c l a1 a 1 h hx45 symb mm inches typ min max typ min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004 so8 drawing is not to scale so8 - 8 lead plastic small outline, 150 mils body width 15/16 ST93CS46, st93cs47
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics - all rights reserved ? microwire is a registered trademark of national semiconductor corp. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 16/16 ST93CS46, st93cs47

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